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Masashi IMAI

Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme Hiroshi SAITO Masashi IMAI Tomohiro YONEDA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1363-1373 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: multi-core systems, task allocation, fault patterns, task scheduling, reliability,
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Signal Propagation Delay Model in Vertically Stacked Chips Nanako NIIOKA Masayuki WATANABE Masa-aki FUKASE Masashi IMAI Atsushi KUROKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2614-2624 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: 3-D IC, delay, through silicon via, sensitivity analysis,
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Novel Implementation Method of Multiple-Way Asynchronous Arbiters Masashi IMAI Tomohiro YONEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1519-1528 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: N-way asynchronous arbiters, asynchronous circuits, mutual exclusion elements, rectangle mesh arbiter, token-ring arbiter,
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High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs Naoya ONIZAWA Akira MOCHIZUKI Hirokatsu SHIRAHAMA Masashi IMAI Tomohiro YONEDA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/06/01 Vol. E97-D No. 6 pp. 1546-1556 Type of Manuscript: PAPER Category: Dependable Computing Keyword: Asynchronous circuits, Network-on-Chip (NoC), burst-mode data transmission, level-encoded dual-rail (LEDR) encoding, error detection, data retransmission,
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Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories Masashi IMAI Tomohiro YONEDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 pp. 1914-1925 Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing) Category: Keyword: mean time to failure, network-on-chip, multiple processor system, fault diagnosis, pair and swap,
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Design Method of High Performance and Low Power Functional Units Considering Delay Variations Kouichi WATANABE Masashi IMAI Masaaki KONDO Hiroshi NAKAMURA Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3519-3528 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: delay variation, dual-rail asynchronous circuit, functional unit, unflip-bit control,
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Evaluation of Checkpointing Mechanism on SCore Cluster System Masaaki KONDO Takuro HAYASHIDA Masashi IMAI Hiroshi NAKAMURA Takashi NANYA Atsushi HORI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2553-2562 Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing) Category: Dependable Software Keyword: checkpointing, rollback-recovery, cluster system, high availability,
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Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design Nattha SRETASEREEKUL Hiroshi SAITO Euiseok KIM Metehan OZCAN Masashi IMAI Hiroshi NAKAMURA Takashi NANYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3028-3037 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: IP Design Keyword: asynchronous controllers, logic synthesis, Control Data Flow Graphs (CDFGs), Signal Transition Graphs (STGs),
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A Cascade ALU Architecture for Asynchronous Super-Scalar Processors Motokazu OZAWA Masashi IMAI Yoichiro UENO Hiroshi NAKAMURA Takashi NANYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 229-237 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: asynchronous, superscalar processor, cascade ALU, fine grain pipeline,
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