Tomohiro YONEDA


Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme
Hiroshi SAITO Masashi IMAI Tomohiro YONEDA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7  pp. 1363-1373
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
multi-core systemstask allocationfault patternstask schedulingreliability
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Novel Implementation Method of Multiple-Way Asynchronous Arbiters
Masashi IMAI Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7  pp. 1519-1528
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
N-way asynchronous arbitersasynchronous circuitsmutual exclusion elementsrectangle mesh arbitertoken-ring arbiter
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High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs
Naoya ONIZAWA Akira MOCHIZUKI Hirokatsu SHIRAHAMA Masashi IMAI Tomohiro YONEDA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/06/01
Vol. E97-D  No. 6  pp. 1546-1556
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
Asynchronous circuitsNetwork-on-Chip (NoC)burst-mode data transmissionlevel-encoded dual-rail (LEDR) encodingerror detectiondata retransmission
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Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories
Masashi IMAI Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9  pp. 1914-1925
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
mean time to failurenetwork-on-chipmultiple processor systemfault diagnosispair and swap
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Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol
Chammika MANNAKKARA Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8  pp. 2145-2161
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
asynchronous pipelinesEarly Acknowledgement protocolbundled-data asynchronous circuits
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A Conservative Framework for Safety-Failure Checking
Frederic BEAL Tomohiro YONEDA Chris J. MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3  pp. 642-654
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Verification and Timing Analysis
Keyword: 
asynchronous circuitsspeed-independent circuitssafety-failure checkinghazard checkingformal verificationover-approximations
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Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times
Hiroshi SAITO Naohiro HAMADA Nattha JINDAPETCH Tomohiro YONEDA Chris MYERS Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12  pp. 2790-2799
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
asynchronous circuitsschedulingstart timesand control steps
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Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation
Tomoya KITAI Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/11/01
Vol. E88-D  No. 11  pp. 2555-2564
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
trace theoretic verificationfailure analysistimed circuitstiming constraints
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Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits
Denduang PRADUBSUWUN Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7  pp. 1646-1661
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
timed trace theorytimed circuitsformal verificationsafety/timing failures
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Partial Order Reduction for Timed Circuit Verification Based on Level Oriented Model
Tomoya KITAI Yusuke OGURO Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2601-2611
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Verification and Dependability Analysis
Keyword: 
Level-oriented modeltimed asynchronous circuitsformal verificationtime Petri nets
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Modular Synthesis of Timed Circuits Using Partial Order Reduction
Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12  pp. 2684-2692
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesispartial order reductiontimed circuitsmodular synthesis
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Framework of Timed Trace Theoretic Verification Revisited
Bin ZHOU Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1595-1604
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Verification
Keyword: 
timed trace theorytrace structurestime Petri netsformal verificationasynchronous circuits
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Formal Verification of Data-Path Circuits Based on Symbolic Simulation
Yoshifumi MORIHIRO Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/06/01
Vol. E85-D  No. 6  pp. 965-974
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
formal verificationsimulationstate transition graphdata pathabstraction
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Implementation of Quasi Delay-Insensitive Boolean Function Blocks
Mrt SAAREPERA Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10  pp. 1879-1889
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
self-timed designFour-Phase signalingdelay-insensitive codecombinational delay-insensitive codequasi-delay-insensitive circuit
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Partial Order Reduction in Symbolic State Space Traversal Using ZBDDs
Minoru TOMISAKA Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/03/25
Vol. E82-D  No. 3  pp. 704-711
Type of Manuscript:  LETTER
Category: Fault Tolerant Computing
Keyword: 
symbolic analysispartial order reductionPetri netsingle place zero reachability problem
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Verification of Scalable-Delay-Insensitive Asynchronous Circuits
Atsushi YAMAZAKI Hiroshi RYU Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/03/25
Vol. E82-D  No. 3  pp. 701-703
Type of Manuscript:  LETTER
Category: Fault Tolerant Computing
Keyword: 
formal verificationasynchronous circuitSDI modelbounded delay model
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CTL Model Checking of Time Petri Nets Using Geometric Regions
Tomohiro YONEDA Hikaru RYUBA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/03/25
Vol. E81-D  No. 3  pp. 297-306
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
CTLmodel checkingtime Petri netsgeometric regionformal verification
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