Framework of Timed Trace Theoretic Verification Revisited

Bin ZHOU  Tomohiro YONEDA  Chris MYERS  

IEICE TRANSACTIONS on Information and Systems   Vol.E85-D   No.10   pp.1595-1604
Publication Date: 2002/10/01
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Verification
timed trace theory,  trace structures,  time Petri nets,  formal verification,  asynchronous circuits,  

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This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.