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IEICE Trans

Keyword : discrete event simulation

NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers
Hideki MIWA Ryutaro SUSUKITA Hidetomo SHIBAMURA Tomoya HIRAO Jun MAKI Makoto YOSHIDA Takayuki KANDO Yuichiro AJIMA Ikuo MIYOSHI Toshiyuki SHIMIZU Yuji OINAGA Hisashige ANDO Yuichi INADOMI Koji INOUE Mutsumi AOYAGI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12 ; pp. 2298-2308
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
discrete event simulation, multiprocessor interconnection, parallel processing, 
 Summary | Full Text:PDF
Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6 ; pp. 1013-1017
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
discrete event simulation, wafer test process, LSI manufacturing, cost, 
 Summary | Full Text:PDF
Effect of 300 mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4 ; pp. 638-645
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
300 mm wafer, lot size, test processing logistics, production dispatching rule scheduling, express lot, cost, final test process, LSI manufacturing, discrete event simulation, 
 Summary | Full Text:PDF
Effect of Express Lots on Production Dispatching Rule Scheduling and Cost in VLSI Manufacturing Final Test Process
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/25
Vol. E82-C  No. 1 ; pp. 86-93
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
production dispatching rule scheduling, express lot, final test cost, final test process, LSI manufacturing, discrete event simulation, 
 Summary | Full Text:PDF
Simulation System for Resource Planning and Line Performance Evaluation of ASIC Manufacturing Lines
Shinji NAKAMURA Chisato HASHIMOTO Akira SHINDO Osamu MORI Junro NOSE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/25
Vol. E79-C  No. 3 ; pp. 290-300
Type of Manuscript:  Special Section PAPER (Special Issue on Scientific ULSI Manufacturing Technology)
Category: CIM/CAM
Keyword: 
LSI manufacturing line, line model, resource planning, discrete event simulation, turnaround time, work-in-process, throughput, 
 Summary | Full Text:PDF