Akihisa CHIKAMURA


Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6  pp. 1013-1017
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
discrete event simulationwafer test processLSI manufacturingcost
 Summary | Full Text:PDF

Effect of 300 mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4  pp. 638-645
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
300 mm waferlot sizetest processing logisticsproduction dispatching rule schedulingexpress lotcostfinal test processLSI manufacturingdiscrete event simulation
 Summary | Full Text:PDF

Effect of Express Lots on Production Dispatching Rule Scheduling and Cost in VLSI Manufacturing Final Test Process
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/25
Vol. E82-C  No. 1  pp. 86-93
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
production dispatching rule schedulingexpress lotfinal test costfinal test processLSI manufacturingdiscrete event simulation
 Summary | Full Text:PDF