Koji NAKAMAE


New Approach of Laser-SQUID Microscopy to LSI Failure Analysis
Kiyoshi NIKAWA Shouji INOUE Tatsuoki NAGAISHI Toru MATSUMOTO Katsuyoshi MIURA Koji NAKAMAE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/03/01
Vol. E92-C  No. 3  pp. 327-333
Type of Manuscript:  INVITED PAPER (Special Section on Recent Progress in Superconducting Analog Devices and Their Applications)
Category: 
Keyword: 
SQUIDlaserLSI chipfailure analysisdefect localization
 Summary | Full Text:PDF

Three-Dimensional Eye Movement Simulator Extracting Instantaneous Eye Movement Rotation Axes, the Plane Formed by Rotation Axes, and Innervations for Eye Muscles
Kanae NAOI Koji NAKAMAE Hiromu FUJIOKA Takao IMAI Kazunori SEKINE Noriaki TAKEDA Takeshi KUBO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/11/01
Vol. E86-D  No. 11  pp. 2452-2462
Type of Manuscript:  PAPER
Category: Medical Engineering
Keyword: 
3D eye movement simulatorcomputer graphicseye movement rotation axisListing's planemuscle innervation
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Automatic LSI Package Lead Inspection System with CCD Camera for Backside Lead Specification
Wataru TAMAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4  pp. 661-667
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
backside LSI package lead inspection systemimage processingQFP packageline-scan CCD camera
 Summary | Full Text:PDF

EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout
Kazuhiro NOMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10  pp. 1564-1570
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: EB Tester
Keyword: 
EB testerline delay faultfault localizationlayout analysiscombinational circuits
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Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6  pp. 1013-1017
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
discrete event simulationwafer test processLSI manufacturingcost
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Effect of 300 mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4  pp. 638-645
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
300 mm waferlot sizetest processing logisticsproduction dispatching rule schedulingexpress lotcostfinal test processLSI manufacturingdiscrete event simulation
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Effect of Express Lots on Production Dispatching Rule Scheduling and Cost in VLSI Manufacturing Final Test Process
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/25
Vol. E82-C  No. 1  pp. 86-93
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
production dispatching rule schedulingexpress lotfinal test costfinal test processLSI manufacturingdiscrete event simulation
 Summary | Full Text:PDF

Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System
Katsuyoshi MIURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3  pp. 498-502
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
bi-directional buscircuit extraction from CAD layoutelectron beam testingLSI
 Summary | Full Text:PDF

Automatic Transistor-Level Performance Fault Tracing by Successive Circuit Extraction from CAD Layout Data for VLSI in the CAD-Linked EB Test System
Katsuyoshi MIURA Koji NAKAMAE hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/11/25
Vol. E78-C  No. 11  pp. 1607-1617
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
performance fault tracingcircuit extraction from CAD layoutelectron beam testingintegrated circuitsvacuum and beam technologies
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Efficient Dynamic Fault Imaging by Fully Utilizing CAD Data in CAD-Linked Electron Beam Test System
Koji NAKAMAE Hirohisa TANAKA Hideharu KUBOTA Hiromu FUJITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4  pp. 546-551
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Failure Analysis)
Category: 
Keyword: 
vacuum and beam technologieselectron beam testingdynamic fault imagingCAD dataimage processing
 Summary | Full Text:PDF

LSI Failure Analysis with CAD-Linked Electron Beam Test System and Its Cost Evaluation
Hiromu FUJIOKA Koji NAKAMAE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4  pp. 535-545
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Failure Analysis)
Category: 
Keyword: 
LSI failure analysiselectron beam testingCAD datacost evaluation
 Summary | Full Text:PDF

Matching of DUT Interconnection Pattern with CAD Layout in CAD-Linked Electron Beam Test System
Koji NAKAMAE Ryo NAKAGAKI Katsuyoshi MIURA Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4  pp. 567-573
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Failure Analysis)
Category: 
Keyword: 
vacuum and beam technologieselectron beam testingpattern matchingCAD layout
 Summary | Full Text:PDF

An Analysis of the Economics of the VLSI Development Including Test Cost
Koji NAKAMAE Homare SAKAMOTO Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A  No. 4  pp. 698-705
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
testing and verificationeconomics of VLSI developmenttest costVLSI development cycleEB testerFIB reconstructionfault modeling
 Summary | Full Text:PDF

Automatic Tracing of Transistor-Level Performance Faults with CAD-Linked Electron Beam Test System
Katsuyoshi MIURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3  pp. 539-545
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
fault analysisfault tracingelectron beam testingperformance faulttransistor-level circuits
 Summary | Full Text:PDF

Function Testing of Bipolar and MOS LSI Circuits with a Combined Stroboscopic SEM-Microcomputer System
Hiromu FUJIOKA Koji NAKAMAE Hiroyuki TAKAOKA Katsumi URA 
Publication:   IEICE TRANSACTIONS (1976-1990)
Publication Date: 1981/05/25
Vol. E64-E  No. 5  pp. 295-301
Type of Manuscript:  PAPER
Category: Semiconductors
Keyword: 
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