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Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA
IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
discrete event simulation, wafer test process, LSI manufacturing, cost,
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Our simulation method by using a combination of discrete event simulation and detailed parametric models of the VLSI manufacturing test system is verified by comparing simulated results with actual ones of a real wafer test facility of one-chip microcomputer in a Japanese semiconductor company. The simulated results are found to be in close agreement with the actual ones. As an application of the verified simulation method, we evaluate the economic effect of the introduction in the wafer test process of LSI testers that allows us to test multiple chips simultaneously. It is found that the optimum number of chips simultaneously tested by an LSI tester is 4 when considering both of the test cost per chip and the average test TAT.