Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-ANo. 7 ;
pp. 1400-1409 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: NBTI, reliability, static timing analysis, timing characterization, aging-aware timing library,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-ANo. 12 ;
pp. 2556-2564 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: single-flux-quantum circuit, static timing analysis, formal verification,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/05/01 Vol. E94-ANo. 5 ;
pp. 1201-1209 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: static timing analysis, gate delay, effective capacitance, non-iterative,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/10/01 Vol. E92-ANo. 10 ;
pp. 2531-2539 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Nonlinear Problems Keyword: static timing analysis, gate delay, effective capacitance, Thevenin model,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-ANo. 12 ;
pp. 3482-3490 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation and Verification Keyword: MTCMOS, selective-MT, static timing analysis, leakage power, delay modeling,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-ANo. 4 ;
pp. 856-864 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: interconnect, worst-case delay, static timing analysis, process variation, capacitance extraction,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-ANo. 12 ;
pp. 3367-3374 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: static timing analysis, gate slew, CMOS inverter, effective capacitance, interconnect loads,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/10/01 Vol. E88-ANo. 10 ;
pp. 2562-2569 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: static timing analysis, gate delay, CMOS inverter, effective capacitance, interconnect loads,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-ANo. 11 ;
pp. 2746-2754 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Analysis Keyword: static timing analysis, statistical approach, correlation, normal distribution, CMOS combinatorial circuits,