Keyword : effective capacitance


A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect
Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Qiang LI Bin LIN Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/05/01
Vol. E94-A  No. 5 ; pp. 1201-1209
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
static timing analysisgate delayeffective capacitancenon-iterative
 Summary | Full Text:PDF

Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model
Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Shuai FANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/10/01
Vol. E92-A  No. 10 ; pp. 2531-2539
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Problems
Keyword: 
static timing analysisgate delayeffective capacitanceThevenin model
 Summary | Full Text:PDF

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
Zhangcai HUANG Atsushi KUROKAWA Jun PAN Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3367-3374
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Prediction and Analysis
Keyword: 
static timing analysisgate slewCMOS invertereffective capacitanceinterconnect loads
 Summary | Full Text:PDF

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads
Zhangcai HUANG Atsushi KUROKAWA Yasuaki INOUE Junfa MAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/10/01
Vol. E88-A  No. 10 ; pp. 2562-2569
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
Category: 
Keyword: 
static timing analysisgate delayCMOS invertereffective capacitanceinterconnect loads
 Summary | Full Text:PDF

A New Three-Piece Driver Model with RLC Interconnect Load
Lakshmi K. VAKATI Kishore K. MUCHHERLA Janet M. WANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/08/01
Vol. E88-A  No. 8 ; pp. 2206-2215
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
inductance criteriaeffective capacitancemulti-ramp driver modelinterconnect model
 Summary | Full Text:PDF

Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design
Norio OHKUBO Takeo YAMASHITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 618-623
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Design Methods and Implementation
Keyword: 
delay calculationeffective capacitancelogic circuit optimizationdelay optimizationLSI design
 Summary | Full Text:PDF