For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/10/01
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications)
static timing analysis, gate delay, CMOS inverter, effective capacitance, interconnect loads,
Full Text: PDF>>
In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.