IEICE Trans

Atsushi KUROKAWA

Signal Propagation Delay Model in Vertically Stacked Chips Nanako NIIOKA Masayuki WATANABE Masa-aki FUKASE Masashi IMAI Atsushi KUROKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2614-2624 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: 3-D IC, delay, through silicon via, sensitivity analysis,
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An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies Li DING Zhangcai HUANG Atsushi KUROKAWA Jing WANG Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/05/01 Vol. E97-A No. 5 pp. 1059-1074 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: gate delay, overshooting effect, multiple-input gates, nanometer technology,
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A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Qiang LI Bin LIN Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/05/01 Vol. E94-A No. 5 pp. 1201-1209 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: static timing analysis, gate delay, effective capacitance, non-iterative,
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Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage Kazuyuki OOYA Yuji TAKASHIMA Atsushi KUROKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/09/01 Vol. E93-A No. 9 pp. 1585-1593 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: IR-drop, power-grid, power-ring, decoupling capacitance, response surface method,
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Impact of Self-Heating in Wire Interconnection on Timing Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 388-392 Type of Manuscript: BRIEF PAPER Category: Keyword: interconnect, delay variation, parasitic resistance, thermal, temperature, self-heat, SoC,
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An Approach for Reducing Leakage Current Variation due to Manufacturing Variability Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3016-3023 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: low power, leakage, gate delay model, variation,
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Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability Yuji TAKASHIMA Kazuyuki OOYA Atsushi KUROKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 2962-2970 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Desing Keyword: redundant via, manufacturing variability, reliability,
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Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Shuai FANG Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/10/01 Vol. E92-A No. 10 pp. 2531-2539 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Nonlinear Problems Keyword: static timing analysis, gate delay, effective capacitance, Thevenin model,
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Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 990-997 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: SSTA, output, transition time, gate delay model, process variation,
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Prevention in a Chip of EMI Noise Caused by X'tal Oscillator Atsushi KUROKAWA Hiroshi FUJITA Tetsuya IBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 1077-1083 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: EMI, crystal oscillator, noise, decoupling capacitor,
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Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3666-3670 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: interconnect, delay variation, parasitic capacitance, SoC,
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Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills Atsushi KUROKAWA Akira KASEBE Toshiki KANAMOTO Yun YANG Zhangcai HUANG Yasuaki INOUE Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 847-855 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: dummy fill, capacitance extraction, capacitance formula, interconnect,
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Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay Zhangcai HUANG Atsushi KUROKAWA Yun YANG Hong YU Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 840-846 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: CMOS inverter, overshooting effect, deep submicron, timing analysis,
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Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 856-864 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: interconnect, worst-case delay, static timing analysis, process variation, capacitance extraction,
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Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance Atsushi KUROKAWA Masanori HASHIMOTO Akira KASEBE Zhangcai HUANG Yun YANG Yasuaki INOUE Ryosuke INAGAKI Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3453-3462 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: capacitance formula, capacitance calculation, capacitance extraction, interconnect capacitance,
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Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills Atsushi KUROKAWA Toshiki KANAMOTO Tetsuya IBE Akira KASEBE Wei Fong CHANG Tetsuro KAGE Yasuaki INOUE Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3471-3478 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: dummy metal, dummy fill, interconnect capacitance, CMP,
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Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew Zhangcai HUANG Atsushi KUROKAWA Jun PAN Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3367-3374 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: static timing analysis, gate slew, CMOS inverter, effective capacitance, interconnect loads,
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Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm Yun YANG Atsushi KUROKAWA Yasuaki INOUE Wenqing ZHAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3412-3420 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Power/Ground Network Keyword: SLP algorithm, GGA method, P/G network optimization, global optimum,
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A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills Atsushi KUROKAWA Toshiki KANAMOTO Akira KASEBE Yasuaki INOUE Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/11/01 Vol. E88-A No. 11 pp. 3180-3187 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: dummy fill, dummy metal, capacitance extraction, interconnect capacitance,
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A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads Zhangcai HUANG Atsushi KUROKAWA Yasuaki INOUE Junfa MAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/10/01 Vol. E88-A No. 10 pp. 2562-2569 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: static timing analysis, gate delay, CMOS inverter, effective capacitance, interconnect loads,
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Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances Atsushi KUROKAWA Takashi SATO Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2933-2941 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: on-chip inductance, parasitic extraction, VLSI interconnects, inductance extraction,
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Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects Atsushi KUROKAWA Kotaro HACHIYA Takashi SATO Kazuya TOKUMASU Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 pp. 841-845 Type of Manuscript: Special Section LETTER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: inductance, parasitic extraction, VLSI interconnect, geometric mean distance, skin effect,
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