IEICE Trans

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IEICE Trans

Takahiro NAGANO

A 6.93-µm² Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory Masataka MINAMI Nagatoshi OHKI Hiroshi ISHIDA Toshiaki YAMANAKA Akihiro SHIMIZU Koichiro ISHIBASHI Akira SATOH Tokuo KURE Takashi NISHIDA Takahiro NAGANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/25 Vol. E80-C No. 4 pp. 590-596 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, full CMOS cell, local interconnect, TiN,
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Driving Source-Line Cell Architecture for Sub-1-V High-Speed Low-Power Applications Hiroyuki MIZUNO Takahiro NAGANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/07/25 Vol. E79-C No. 7 pp. 963-968 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
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A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits Hisayuki HIGUCHI Suguru TACHIBANA Masataka MINAMI Takahiro NAGANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 pp. 757-762 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Static RAMs Keyword: TLB, CAM, low power, fully associative,
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A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers Koichiro ISHIBASHI Koichi TAKASUGI Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Toshiaki YAMANAKA Akira FUKAMI Naotaka HASHIMOTO Nagatoshi OHKI Akihiro SHIMIZU Takashi HASHIMOTO Takahiro NAGANO Takashi NISHIDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/06/25 Vol. E78-C No. 6 pp. 728-734 Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995)) Category: Keyword:
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