A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits

Hisayuki HIGUCHI  Suguru TACHIBANA  Masataka MINAMI  Takahiro NAGANO  

IEICE TRANSACTIONS on Electronics   Vol.E79-C   No.6   pp.757-762
Publication Date: 1996/06/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
TLB,  CAM,  low power,  fully associative,  

Full Text: PDF>>
Buy this Article

Low-power, high-speed match-detection circuits for a content addressable memory(CAM) are proposed and evaluated. The circuits consist a current supply to a match-line, a differential amplifier, and 9-MOSFET CAM cells. The implementation of these circuits made it possible to realize a 16-entry, 32-bit data-compare CAM TEG of 1.2-ns matchdetection time with 5-mW power dissipation in 10-ns cycle-time.