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Driving Source-Line Cell Architecture for Sub-1-V High-Speed Low-Power Applications
Hiroyuki MIZUNO Takahiro NAGANO
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
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A novel SRAM cell architecture for sub-1-V high-speed operation is proposed operation is proposed that uses neither low-Vth MOSFET's nor modified cell layout patterns. A source-line, connected to the source terminals of the driver MOSFET's is controlled so that it is negative and floating in the read and write cycles, respectively. This improved the bit-line access time by 1/4-1/2 at supply voltages of 0.5-1.0 V. Limiting the bit-line swing reduces by 1/10 the writing power needed to charge them and allows faster write-recovery, as well. The achievability of low-power 100-MHz operation over a wide range of supply voltages is demonstrated.