A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers

Koichiro ISHIBASHI
Koichi TAKASUGI
Kunihiro KOMIYAJI
Hiroshi TOYOSHIMA
Toshiaki YAMANAKA
Akira FUKAMI
Naotaka HASHIMOTO
Nagatoshi OHKI
Akihiro SHIMIZU
Takashi HASHIMOTO
Takahiro NAGANO
Takashi NISHIDA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E78-C    No.6    pp.728-734
Publication Date: 1995/06/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
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Summary: 
A 4-Mb CMOS SRAM with 3.84 µm2 TFT load cells is fabricated using 0.25-µm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells.