Koichi TAKASUGI


A 2.6-ns Wave-Pipelined CMOS SRAM with Dual-Sensing-Latch Circuits
Suguru TACHIBANA Hisayuki HIGUCHI Koichi TAKASUGI Katsuro SASAKI Toshiaki YAMANAKA Yoshinobu NAKAGOME 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 735-738
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
 Summary | Full Text:PDF

A 6-ns 4-Mb CMOS SRAM with Offset-Voltage-Insensitive Current Sense Amplifiers
Koichiro ISHIBASHI Koichi TAKASUGI Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Toshiaki YAMANAKA Akira FUKAMI Naotaka HASHIMOTO Nagatoshi OHKI Akihiro SHIMIZU Takashi HASHIMOTO Takahiro NAGANO Takashi NISHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/06/25
Vol. E78-C  No. 6  pp. 728-734
Type of Manuscript:  Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))
Category: 
Keyword: 
 Summary | Full Text:PDF