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| Nobutaro SHIBATA
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A SOI Cache-Tag Memory with Dual-Rail Wordline Scheme
Nobutaro SHIBATA Takako ISHIHARA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2016/02/01
Vol. E99-C
No. 2
pp. 316-330
Type of Manuscript:
PAPER
Category: Integrated Electronics
Keyword:
4-way set-associative, cache-tag, CMOS, directed graph, dual-rail wordline, FD-SOI, I/O-separated memory cell, LRU, NRZ-type write-enable signal, SIMOX, SRAM, | | | Summary | Full Text:PDF | |
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A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits
Nobutaro SHIBATA Mayumi WATANABE | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C
No. 7
pp. 797-804
Type of Manuscript:
Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category:
Keyword:
marcocell, memory, synchronous, low power, latch type, | | | Summary | Full Text:PDF | |
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