Keyword : plain CMOS logic

An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines
Nobutaro SHIBATA Mitsuo NAKAMURA 
Publication:   
Publication Date: 2018/08/01
Vol. E101-A  No. 8 ; pp. 1185-1196
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
ATE, delay-locked loop, digital-to-time converter, linearity error, on the fly, plain CMOS logic, timing jitter, timing vernier, 
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