|
| Atsushi TAKAHASHI
| |
|
|
Gridless Gap Channel Routing with Variable-Width Wires
Masayuki SHIMODA Atsushi TAKAHASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/03/01
Vol. E108-A
No. 3
pp. 517-524
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
gridless channel routing, variable-width wire, | | | Summary | Full Text:PDF | |
| |
|
| |
|
| |
|
|
A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections
Shimpei SATO Kano AKAGI Atsushi TAKAHASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2020/09/01
Vol. E103-A
No. 9
pp. 1037-1044
Type of Manuscript:
Special Section PAPER (Special Section on Circuits and Systems)
Category:
Keyword:
routing algorithm, set-pair routing problem, PCB, interposer, | | | Summary | Full Text:PDF | |
| |
|
| |
|
| |
|
|
A Length Matching Routing Algorithm for Set-Pair Routing Problem
Yuta NAKATANI Atsushi TAKAHASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A
No. 12
pp. 2565-2571
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
set-pair routing, interposer, PCB, routing algorithm, | | | Summary | Full Text:PDF | |
| |
|
| |
|
| |
|
|
FOREWORD
Atsushi TAKAHASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12
pp. 2481-2481
Type of Manuscript:
FOREWORD
Category:
Keyword:
| | | Summary | Full Text:PDF | |
| |
|
|
CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles
Yukihide KOHIRA Atsushi TAKAHASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A
No. 12
pp. 2380-2388
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
PCB routing, length-matching routing, trunk routing, | | | Summary | Full Text:PDF | |
| |
|
| |
|
| |
|
|
Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework
Yukihide KOHIRA Shuhei TANI Atsushi TAKAHASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A
No. 4
pp. 1106-1114
Type of Manuscript:
Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
delay insertion, clock scheduling, general-synchronous framework, | | | Summary | Full Text:PDF | |
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages
Yoichi TOMIOKA Atsushi TAKAHASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A
No. 12
pp. 3551-3559
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword:
ball grid array, monotonic, single-layer, package, routing, | | | Summary | Full Text:PDF | |
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
Clock Schedule Design for Minimum Realization Cost
Tomoyuki YODA Atsushi TAKAHASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A
No. 12
pp. 2552-2557
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword:
semi-synchronous circuit, clock schedule, clock tree, | | | Summary | Full Text:PDF | |
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
| |
|
|
A Switch-Box Router  BOX-PEELER" and Its Tractable Problems
Atsushi TAKAHASHI Yoji KAJITANI | Publication: IEICE TRANSACTIONS (1976-1990)
Publication Date: 1989/12/25
Vol. E72-E
No. 12
pp. 1367-1373
Type of Manuscript:
Special Section PAPER (Special Issue on the 2nd Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology
Keyword:
| | | Summary | Full Text:PDF | |
|
|