A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework

Yukihide KOHIRA  Atsushi TAKAHASHI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E91-A   No.10   pp.3030-3037
Publication Date: 2008/10/01
Online ISSN: 1745-1337
DOI: 10.1093/ietfec/e91-a.10.3030
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
register relocation,  retiming,  clock scheduling,  general-synchronous framework,  

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Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation while maintaining the circuit behavior and topology. However, if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits.