Tomoyuki YODA


Clock Schedule Design for Minimum Realization Cost
Tomoyuki YODA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12  pp. 2552-2557
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword: 
semi-synchronous circuitclock scheduleclock tree
 Summary | Full Text:PDF

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
Tomoyuki YODA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11  pp. 2383-2389
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
delay insertionclock period minimizationsemi-synchronous circuit
 Summary | Full Text:PDF