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Vol.E76-C No.7
pp.1080-1093
Special SectionPAPER
Improved Binary Digital Architectures
Speculative Execution and Reducing Branch Penalty on a Superscalar Processor
Hideki ANDO, Chikako NAKANISHI, Hirohisa MACHIDA, Tetsuya HARA, Masao NAKAYA, |
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Vol.E76-C No.7
pp.1094-1101
Special SectionPAPER
Improved Binary Digital Architectures
A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs
Harufusa KONDOH, Hiromi NOTANI, Hideaki YAMANAKA, Keiichi HIGASHITANI, Hirotaka SAITO, Isamu HAYASHI, Yoshio MATSUDA, Kazuyoshi OSHIMA, Masao NAKAYA, |
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Vol.E76-C No.7
pp.1102-1111
Special SectionPAPER
Fuzzy Logic System
A 12-bit Resolution 200 kFLIPS Fuzzy Inference Processor
Kazuo NAKAMURA, Narumi SAKASHITA, Yasuhiko NITTA, Kenichi SHIMOMURA, Takeshi TOKUDA, |
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Vol.E76-C No.7
pp.1112-1118
Special SectionPAPER
Multiple-Valued Architectures and Systems
Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel k-Ary Operation Circuits
Saneaki TAMAKI, Michitaka KAMEYAMA, |
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Vol.E76-C No.7
pp.1119-1125
Special SectionPAPER
Multiple-Valued Architectures and Systems
Design of Highly Parallel Linear Digital System for ULSI Processors
Masami NAKAJIMA, Michitaka KAMEYAMA, |
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Vol.E76-C No.7
pp.1126-1132
Special SectionPAPER
Multiple-Valued Architectures and Systems
Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model
Takahiro HANYU, Yoshikazu YABE, Michitaka KAMEYAMA, |
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Vol.E76-C No.7
pp.1133-1143
Special SectionPAPER
Multiple-Valued Architectures and Systems
Design of Wave-Parallel Computing Architectures and Its Application to Massively Parallel Image Processing
Yasushi YUMINAKA, Takafumi AOKI, Tatsuo HIGUCHI, |
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Vol.E76-C No.7
pp.1144-1150
Special SectionPAPER
Memory-Based Parallel Processor Architectures
IMAP: Integrated Memory Array Processor--Toward a GIPS Order SIMD Processing LSI--
Yoshihiro FUJITA, Nobuyuki YAMASHITA, Shin'ichiro OKAZAKI, |
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Vol.E76-C No.7
pp.1151-1158
Special SectionPAPER
Memory-Based Parallel Processor Architectures
A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture
Kazutoshi KOBAYASHI, Keikichi TAMARU, Hiroto YASUURA, Hidetoshi ONODERA, |
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Vol.E76-C No.7
pp.1159-1166
Special SectionPAPER
Neural Networks and Chips
Hardware Architecture for Kohonen Network
Hidetoshi ONODERA, Kiyoshi TAKESHITA, Keikichi TAMARU, |
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Summary | Full Text:PDF | |
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