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Vol.E80-D No.3
pp.285-286 FOREWORD
FOREWORD Takashi NANYA, |
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Vol.E80-D No.3
pp.287-295 Special SectionPAPER
Design High Performance Two-Phase Asynchronous Pipelines Sam APPLETON, Shannon MORTON, Michael LIEBELT, |
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Vol.E80-D No.3
pp.296-307 Special SectionPAPER
Design An Asynchronous Cell Library for Self-Timed System Designs Yuk-Wah PANG, Wing-yun SIT, Chiu-sing CHOY, Cheong-fat CHAN, Wai-kuen CHAM, |
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Vol.E80-D No.3
pp.308-314 Special SectionPAPER
Specification Description Statechart Methodology for the Design, Validation, and Synthesis of Large Scale Asynchronous Systems Rakefet KOL, Ran GINOSAR, Goel SAMUEL, |
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Vol.E80-D No.3
pp.315-325 Special SectionPAPER
Synthesis Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers Jordi CORTADELLA, Michael KISHINEVSKY, Alex KONDRATYEV, Luciano LAVAGNO, Alexandre YAKOVLEV, |
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Vol.E80-D No.3
pp.326-335 Special SectionPAPER
Synthesis Synthesis of Asynchronous Circuits from Signal Transition Graph Specifications Sung-Bum PARK, Takashi NANYA, |
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Vol.E80-D No.3
pp.336-343 Special SectionPAPER
Synthesis On Deriving Logic Functions of Asynchronous Circuits by STG Unfoldings Toshiyuki MIYAMOTO, Sadatoshi KUMAGAI, |
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Vol.E80-D No.3
pp.344-350 Special SectionPAPER
Completion-Detection & Checking Completion-Detection Techniques for Asynchronous Circuits Eckhard GRASS, Viv BARTLETT, Izzet KALE, |
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Vol.E80-D No.3
pp.351-362 Special SectionPAPER
Completion-Detection & Checking On Concurrent Error Detection of Asynchronous Circuits Using Mixed-Signal Approach B. Ravi KISHORE, Takashi NANYA, |
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Vol.E80-D No.3
pp.363-370 PAPER
Software Theory The Completeness of Order-Sorted Term Rewriting Systems Is Preserved by Currying Yoshinobu KAWABE, Naohiro ISHII, |
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Current List: 36691 - 36700
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