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Vol.E80-C No.3
pp.431-435
Special SectionPAPER
Study on Parasitic Bipolar Effect in a 200-V-Class Power MOSFET Using Silicon Direct Bonding SOI Wafer
Satoshi MATSUMOTO, Toshiaki YACHI, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.3
pp.436-442
INVITED PAPER
Circuit Technologies and Applications
Circuit Technology for Giga-bit/Low Voltage Operating SOI-DRAM
Akihiko YASUOKA, Kazutami ARIMOTO, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.3
pp.443-454
INVITED PAPER
Circuit Technologies and Applications
The Potential of Ultrathin-Film SOI Devices for Low-Power and High-Speed Applications
Yuichi KADO, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.3
pp.455-463
Special SectionPAPER
A Fully Depleted CMOS/SIMOX LSI Scheme Using a LVTTL-Compatible and Over-2, 000-V ESD-Hardness I/O Circuit for Reduction in Active and Static Power Consumption
Yusuke OHTOMO, Takeshi MIZUSAWA, Kazuyoshi NISHIMURA, Hirotoshi SAWADA, Masayuki INO, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.3
pp.464-471
Special SectionPAPER
Analysis of the Delay Distributions of 0.5 µm SOI LSIs
Toshiaki IWAMATSU, Takashi IPPOSHI, Yasuo YAMAGUCHI, Kimio UEDA, Koichiro MASHIKO, Shigeto MAEGAWA, Yasuo INOUE, Tadashi HIRAO, Tdashi NISHIMURA, Akihiko YASUOKA, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.3
pp.472-477
Special SectionPAPER
An Ultra Low Voltage SOI CMOS Pass-Gate Logic
Tsuneaki FUSE, Yukihito OOWAKI, Mamoru TERAUCHI, Shigeyoshi WATANABE, Makoto YOSHIMI, Kazunori OHUCHI, Jun'ichi MATSUNAGA, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.3
pp.478-488
PAPER
Electronic Circuits
Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic
Tsz-Shing CHEUNG, Kunihiro ASADA, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.3
pp.489-497
PAPER
Semiconductor Materials and Devices
1200 Dots-Per-Inch Light Emitting Diode Array Fabricated by Solid-Phase Zinc Diffusion
Mitsuhiko OGIHARA, Takatoku SHIMIZU, Masumi TANINAKA, Yukio NAKAMURA, Ichimatsu ABIKO, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.3
pp.498-502
LETTER
Integrated Electronics
Hierarchical Fault Tracing for VLSIs with Bi-directional Busses from CAD Layout Data in the CAD-Linked EB Test System
Katsuyoshi MIURA, Koji NAKAMAE, Hiromu FUJIOKA, |
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Summary | Full Text:PDF | |
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Vol.E80-C No.3
pp.503-507
LETTER
Electromagnetic Theory
On the Applicability of a Boundary Matching Technique to the Reconstruction of Circularly Symmetric Cylinders from Scattered H-Wave
Kenichi ISHIDA, Mitsuo TATEIBA, |
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Summary | Full Text:PDF | |
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