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IEICE Trans

Keyword : production dispatching rule scheduling

Effect of 300 mm Wafer Transition and Test Processing Logistics on VLSI Manufacturing Final Test Process Efficiency and Cost
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4 ; pp. 638-645
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
300 mm wafer, lot size, test processing logistics, production dispatching rule scheduling, express lot, cost, final test process, LSI manufacturing, discrete event simulation, 
 Summary | Full Text:PDF
Effect of Express Lots on Production Dispatching Rule Scheduling and Cost in VLSI Manufacturing Final Test Process
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/25
Vol. E82-C  No. 1 ; pp. 86-93
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
production dispatching rule scheduling, express lot, final test cost, final test process, LSI manufacturing, discrete event simulation, 
 Summary | Full Text:PDF