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| Keyword : multiplier
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A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source
Kazuhiro SHOUNO Tasuku HORI Yukio ISHIBASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A
No. 6 ;
pp. 1533-1539
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category:
Keyword:
CMOS, analog, transconductor, multiplier, mobility, | | | Summary | Full Text:PDF | |
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Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation
Jung-Yeol OH Myoung-Seob LIM | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2006/04/01
Vol. E89-B
No. 4 ;
pp. 1425-1429
Type of Manuscript:
LETTER
Category: Devices/Circuits for Communications
Keyword:
FFT, radix-24, radix-22, SDF, CSD, multiplier, | | | Summary | Full Text:PDF | |
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New Radix-2 to the 4th Power Pipeline FFT Processor
Jung-Yeol OH Myoung-Seob LIM | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C
No. 8 ;
pp. 1740-1746
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category:
Keyword:
FFT, radix, pipeline, SDF, CSD, multiplier, | | | Summary | Full Text:PDF | |
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A New Algorithm for the Configuration of Fast Adder Trees
Alberto PALACIOS-PAWLOVSKY | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A
No. 12 ;
pp. 2426-2430
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword:
multiplier, adder, Wallace tree, partial product addition, Dadda tree, | | | Summary | Full Text:PDF | |
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A Charge-Domain D/A Conversion System
Yasuo NAGAZUMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/02/25
Vol. E79-A
No. 2 ;
pp. 217-223
Type of Manuscript:
Special Section PAPER (Special Section on Analog Technologies in Submicron Era)
Category:
Keyword:
CCD, multiplier, MDAC, DCT, image processing, | | | Summary | Full Text:PDF | |
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An MOS Operational Transconductance Amplifier and an MOS Four-Quadrant Analog Multiplier Using the Quadritail Cell
Katsuji KIMURA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A
No. 12 ;
pp. 1774-1776
Type of Manuscript:
Special Section LETTER (Special Section on the 1992 IEICE Fall Conference)
Category:
Keyword:
OTA, multiplier, transconductance, quadritail cell, MOS, LSI, | | | Summary | Full Text:PDF | |
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4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic