A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier

Nobutaka KITO  Kensuke HANAI  Naofumi TAKAGI  

IEICE TRANSACTIONS on Information and Systems   Vol.E93-D   No.10   pp.2783-2791
Publication Date: 2010/10/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E93.D.2783
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Information Network
multiplier,  design for testability,  4-2 adder tree,  C-testability,  

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A C-testable 4-2 adder tree for an easily testable high-speed multiplier is proposed, and a recursive method for test generation is shown. By using the specific patterns that we call 'alternately inverted patterns,' the adder tree, as well as partial product generators, can be tested with 14 patterns regardless of its operand size under the cell fault model. The test patterns are easily fed through the partial product generators. The hardware overhead of the 4-2 adder tree with partial product generators for a 64-bit multiplier is about 15%. By using a previously proposed easily testable adder as the final adder, we can obtain an easily testable high-speed multiplier.