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IEICE Trans

Shoichi MASUI

FOREWORD
Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2017/06/01
Vol. E100-C  No. 6  pp. 513-514
Type of Manuscript:  FOREWORD
Category: 
Keyword: 
 Summary | Full Text:PDF
Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers
Jun Gyu LEE Zule XU Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8  pp. 1337-1346
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
phase-locked loop, frequency synthesizer, loop design, settling time, process variations, 
 Summary | Full Text:PDF
Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL
Zule XU Jun Gyu LEE Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6  pp. 1065-1068
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
digital delta-sigma modulator (DDSM), fractional-N PLL, dither, 
 Summary | Full Text:PDF
Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology
Takayuki KONISHI Kenji INAZU Jun Gyu LEE Masanori NATSUI Shoichi MASUI Boris MURMANN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3  pp. 334-345
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
operational transconductance amplifier, design optimization, analog design methodology, low power design, 
 Summary | Full Text:PDF
Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers
Hideaki KONDO Masaru SAWADA Norio MURAKAMI Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/10/01
Vol. E92-C  No. 10  pp. 1304-1310
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
tunable filter, bandpass filter, calibration, radio receiver, frequency control, 
 Summary | Full Text:PDF
A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory
Shoichi MASUI Toshiyuki TERAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 601-607
Type of Manuscript:  INVITED PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: 
Keyword: 
radio frequency identification, wireless communication, nonvolatile memory, ferroelectric random access memory, low power design, 
 Summary | Full Text:PDF
Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm
Shoichi MASUI Kenji MUKAIDA Masahiko TAKENAKA Naoya TORII 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 576-581
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
public key cryptosystem, RSA algorithm, Montgomery algorithm, modular multiplication, multiplier-accumulator, 
 Summary | Full Text:PDF
Design and Application of Ferroelectric Memory Based Nonvolatile SRAM
Shoichi MASUI Tsuzumi NINOMIYA Takashi OHKAWA Michiya OURA Yoshimasa HORII Nobuhiro KIN Koichiro HONDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11  pp. 1769-1776
Type of Manuscript:  INVITED PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
ferroelectric material, nonvolatile memory, programming, SoC, programmable logic devices, 
 Summary | Full Text:PDF
Evaluation of Fixed Charge and Interface Trap Densities in SIMOX Wafers and Their Effects on Device Characteristics
Shoichi MASUI Tatsuo NAKAJIMA Keisuke KAWAMURA Takayuki YANO Isao HAMAGUCHI Masaharu TACHIMORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/09/25
Vol. E78-C  No. 9  pp. 1263-1272
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SOI, fixed oxide charge, interface trap, parasitic capacitance, subthreshold slope, 
 Summary | Full Text:PDF
Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits
David K. SU Marc J. LOINAZ Shoichi MASUI Bruce A. WOOLEY 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C  No. 5  pp. 760-770
Type of Manuscript:  Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
Category: 
Keyword: 
 Summary | Full Text:PDF