Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology

Takayuki KONISHI  Kenji INAZU  Jun Gyu LEE  Masanori NATSUI  Shoichi MASUI  Boris MURMANN  

IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.3   pp.334-345
Publication Date: 2011/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.334
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
operational transconductance amplifier,  design optimization,  analog design methodology,  low power design,  

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We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125 MS/s pipeline A/D converter implemented in a 0.18 µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.