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IEICE Trans

Hiroki SUTOH

A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C  No. 7  pp. 1334-1340
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLL, CMOS/SIMOX, VCO, clock, jitter, skew, lock range, 
 Summary | Full Text:PDF
A Clock Distribution Technique with an Automatic Skew Compensation Circuit
Hiroki SUTOH Kimihiro YAMAKOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/02/25
Vol. E81-C  No. 2  pp. 277-283
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock skew, clock distribution, compensation, variable delay line, CMOS, 
 Summary | Full Text:PDF
A 31 GHz Static Frequency Divider Using Au/WSiN Gate GaAs MESFETs
Masami TOKUMITSU Kiyomitsu ONODERA Hiroki SUTOH Kazuyoshi ASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1991/12/25
Vol. E74-C  No. 12  pp. 4136-4140
Type of Manuscript:  Special Section PAPER (Special Issue on Millimeter-Wave/Heterojunction Devices)
Category: 
Keyword: 
 Summary | Full Text:PDF