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A Clock Distribution Technique with an Automatic Skew Compensation Circuit
Hiroki SUTOH Kimihiro YAMAKOSHI
IEICE TRANSACTIONS on Electronics
Publication Date: 1998/02/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
clock skew, clock distribution, compensation, variable delay line, CMOS,
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This paper describes a low-skew clock distribution technique for multiple targets. An automatic skew compensation circuit, that detects the round-trip delay through a pair of matched interconnection lines and corrects the delay of the variable delay lines, maintains clock skew and delay from among multiple targets below the resolution time of the variable delay lines without any manual adjustment. Measured results show that the initial clock skew of 900 ps is automatically reduced to 30 ps at a clock frequency of up to 250 MHz with 60 ps of clock jitter. Moreover, they show that the initial clock delay of 1500 ps is cancelled and 60 ps of clock delay can be achieved. The power dissipation is 100 mW at 250 MHz.