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Vol.E78-D No.7
pp.802-810
Special SectionPAPER
A New Conformance Testing Technique for Localization of Multiple Faults in Communication Protocols
Yoshiaki KAKUDA, Hideki YUKITOMO, Shinji KUSUMOTO, Tohru KIKUNO, |
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Summary | Full Text:PDF | |
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Vol.E78-D No.7
pp.811-816
Special SectionPAPER
Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis
Seiji KAJIHARA, Rikiya NISHIGAYA, Tetsuji SUMIOKA, Kozo KINOSHITA, |
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Summary | Full Text:PDF | |
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Vol.E78-D No.7
pp.817-821
Special SectionPAPER
A Single Bridging Fault Location Technique for CMOS Combinational Circuits
Koji YAMAZAKI, Teruhiko YAMADA, |
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Summary | Full Text:PDF | |
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Vol.E78-D No.7
pp.822-829
Special SectionPAPER
A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects
Xiangqiu YU, Hiroshi TAKAHASHI, Yuzo TAKAMATSU, |
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Summary | Full Text:PDF | |
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Vol.E78-D No.7
pp.830-838
Special SectionPAPER
Testing of k-FR Circuits under Highly Observable Condition
Xiaoqing WEN, Hideo TAMAMOTO, Kozo KINOSHITA, |
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Summary | Full Text:PDF | |
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Vol.E78-D No.7
pp.839-844
Special SectionPAPER
The Effect of CMOS VLSI IDDq Measurement on Defect Level
Junichi HIRASE, Masanori HAMADA, |
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Summary | Full Text:PDF | |
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Vol.E78-D No.7
pp.845-852
Special SectionPAPER
A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs
Yukiya MIURA, Sachio NAITO, |
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Summary | Full Text:PDF | |
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Vol.E78-D No.7
pp.853-860
Special SectionPAPER
Very Fast Fault Simulation for Voltage Stuck-at Faults in Analog/Digital Mixed Circuit
Shigeharu TESHIMA, Naoya CHUJO, Ryuta TERASHIMA, |
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Summary | Full Text:PDF | |
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Vol.E78-D No.7
pp.861-867
Special SectionPAPER
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement
Hiroyuki YOTSUYANAGI, Seiji KAJIHARA, Kozo KINOSHITA, |
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Summary | Full Text:PDF | |
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Vol.E78-D No.7
pp.868-873
Special SectionPAPER
A Practical Test System with a Fuzzy Logic Controller
Takeshi KOYAMA, Ryuji OHMURA, |
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Summary | Full Text:PDF | |
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Current List: 38431 - 38440
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