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Vol.E78-C No.7
pp.773-781
INVITED PAPER
Emerging Memory Solutions for Graphics Applications
Katsumi SUIZU, Toshiyuki OGAWA, Kazuyasu FUJISHIMA, |
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Summary | Full Text:PDF | |
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Vol.E78-C No.7
pp.782-788
Special SectionPAPER
A Synchronous DRAM with New High-Speed I/O Lines Method for the MultiMedia Age
Yuji SAKAI, Kanji OISHI, Miki MATSUMOTO, Shoji WADA, Tadamichi SAKASHITA, Masahiro KATAYAMA, |
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Summary | Full Text:PDF | |
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Vol.E78-C No.7
pp.789-796
Special SectionPAPER
NAND-Structured Trench Capacitor Cell Technologies for 256 Mb DRAM and Beyond
Takeshi HAMAMOTO, Yutaka ISHIBASHI, Masami AOKI, Yoshihiko SAITOH, Takashi YAMADA, |
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Summary | Full Text:PDF | |
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Vol.E78-C No.7
pp.797-804
Special SectionPAPER
A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits
Nobutaro SHIBATA, Mayumi WATANABE, |
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Summary | Full Text:PDF | |
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Vol.E78-C No.7
pp.805-811
Special SectionPAPER
PLL Timing Design Techniques for Large-Scale, High-Speed, Low-Power, Low-Cost SRAMs
Kazuyuki NAKAMURA, Shigeru KUHARA, Thoru KIMURA, Masahide TAKADA, Hisamitsu SUZUKI, Hiroshi YOSHIDA, Tohru YAMAZAKI, |
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Summary | Full Text:PDF | |
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Vol.E78-C No.7
pp.812-817
Special SectionPAPER
Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
Yasuo YAMAGUCHI, Jun TAKAHASHI, Takehisa YAMAGUCHI, Tomohisa WADA, Toshiaki IWAMATSU, Hans-Oliver JOACHIM, Yasuo INOUE, Tadashi NISHIMURA, Natsuro TSUBOUCHI, |
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Summary | Full Text:PDF | |
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Vol.E78-C No.7
pp.818-824
Special SectionPAPER
A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture
Hiromi NOBUKATA, Kenichi SATORI, Shinji HIRAMATSU, Hideki ARAKAWA, |
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Summary | Full Text:PDF | |
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Vol.E78-C No.7
pp.825-831
Special SectionPAPER
Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
Hiroshi SUGAWARA, Toshio TAKESHIMA, Hiroshi TAKADA, Yoshiaki S. HISAMUNE, Kohji KANAMORI, Takeshi OKAZAWA, Tatsunori MUROTANI, Isao SASAKI, |
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Summary | Full Text:PDF | |
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Vol.E78-C No.7
pp.832-837
Special SectionPAPER
Programming and Program-Verification Methods for Low-Voltage Flash Memories Using a Sector Programming Scheme
Katsutaka KIMURA, Toshihiro TANAKA, Masataka KATO, Tetsuo ADACHI, Keisuke OGURA, Hitoshi KUME, |
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Summary | Full Text:PDF | |
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Vol.E78-C No.7
pp.838-844
Special SectionPAPER
BIST Circuit Macro Using Microprogram ROM for LSI Memories
Hiroki KOIKE, Toshio TAKESHIMA, Masahide TAKADA, |
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Summary | Full Text:PDF | |
| Current List: 38411 - 38420
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