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Vol.E78-C No.7
pp.845-851
Special SectionPAPER
New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell
Yukihito OOWAKI, Keiji MABUCHI, Shigeyoshi WATANABE, Kazunori OHUCHI, Jun'ichi MATSUNAGA, Fujio MASUOKA, |
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Vol.E78-C No.7
pp.852-857
Special SectionPAPER
Use of a Monte Carlo Wiring Yield Simulator to Optimize Design of Random Logic Circuits for Yield Enhancement
Hideyuki FUKUHARA, Takao KOMATSUZAKI, Katsushi BOKU, Yoichi MIYAI, |
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Vol.E78-C No.7
pp.858-865
PAPER
Integrated Electronics
Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
Tadaaki YAMAUCHI, Koji TANAKA, Kiyohiro FURUTANI, Yoshikazu MOROOKA, Hiroshi MIYAMOTO, Hideyuki OZAKI, |
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Vol.E78-C No.7
pp.866-872
PAPER
Integrated Electronics
3.0 Gb/s, 272 mW, 8:1 Multiplexer and 4.1 Gb/s, 388 mW, 1:8 Demultiplexer
Kimio UEDA, Nagisa SASAKI, Hisayasu SATO, Shunji KUBO, Koichiro MASHIKO, |
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Vol.E78-C No.7
pp.873-877
PAPER
Superconductive Electronics
Frequency-Dependent Finite-Difference Time-Domain Analysis of High-Tc Superconducting Asymmetric Coplanar Strip Line
Masafumi HIRA, Yasunobu MIZOMOTO, Sadao KURAZONO, |
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Vol.E78-C No.7
pp.878-884
PAPER
Electronic Displays
Analysis on Reduction of the Temperature Rise of Deflection Yoke (DY)
Rensi MOROOKA, Yukitoshi INOUE, Katsuhiko SHIOMI, |
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Vol.E78-C No.7
pp.885-886
LETTER
Opto-Electronics
Fiber Optic Temperature Sensor Using Two Modes by Holographic Filter
Manabu YOSHIKAWA, Kazuo ASAKAWA, |
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Vol.E78-D No.7
pp.789-790
FOREWORD
FOREWORD
Hideo FUJIWARA, |
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Vol.E78-D No.7
pp.791-795
Special SectionPAPER
Towards Verification of Bit-Slice Circuits--Time-Space Modal Model Checking Approach--
Hiromi HIRAISHI, |
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Vol.E78-D No.7
pp.796-801
Special SectionPAPER
Temporal Verification of Real-Time Systems
Sérgio V. CAMPOS, Edmund M. CLARKE, Wilfredo MARRERO, Marius MINEA, Hiromi HIRAISHI, |
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Summary | Full Text:PDF | |
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