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IEICE Trans

Keyword : two-pattern testing

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2 ; pp. 269-282
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test compression, statistical coding, run-length coding, delay fault testing, two-pattern testing, scan testing, 
 Summary | Full Text:PDF
Scan Design for Two-Pattern Test without Extra Latches
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12 ; pp. 2777-2785
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testing, delay fault testing, scan design, enhanced scan, 
 Summary | Full Text:PDF
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/09/01
Vol. E88-D  No. 9 ; pp. 2135-2142
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testing, adjacency test, deterministic test generation, BIST, 
 Summary | Full Text:PDF
Two-Pattern Test Capabilities of Autonomous TGP Circuits
Kiyoshi FURUYA Edward J. McCLUSKEY 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 800-808
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
two-pattern testing, built-in self-test, TPG circuit, linear sequential circuit, transition coverage, 
 Summary | Full Text:PDF