Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding

Kazuteru NAMBA  Hideo ITO  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E92-D   No.2   pp.269-282
Publication Date: 2009/02/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E92.D.269
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
test compression,  statistical coding,  run-length coding,  delay fault testing,  two-pattern testing,  scan testing,  

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Summary: 
This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).