Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-ANo. 12 ;
pp. 3128-3135 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: test generation, transistor defects, stuck-at tests, defect coverage,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-ANo. 12 ;
pp. 3506-3513 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: fault simulation, test generation, stuck-open faults, stuck-at tests, defect coverage,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/25 Vol. E81-DNo. 7 ;
pp. 749-752 Type of Manuscript: Special Section LETTER (Special Issue on Test and Diagnosis of VLSI) Category: Keyword: Josephson logic circuit, test, defect coverage,