Keyword : defect coverage


Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3128-3135
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
test generationtransistor defectsstuck-at testsdefect coverage
 Summary | Full Text:PDF

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3506-3513
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
fault simulationtest generationstuck-open faultsstuck-at testsdefect coverage
 Summary | Full Text:PDF

On Testing of Josephson Logic Circuits Composed of the 4JL Gates
Teruhiko YAMADA Tsuyoshi SASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 749-752
Type of Manuscript:  Special Section LETTER (Special Issue on Test and Diagnosis of VLSI)
Category: 
Keyword: 
Josephson logic circuittestdefect coverage
 Summary | Full Text:PDF