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IEICE Trans

Keyword : wafer test process

Verification of Wafer Test Process Simulation in VLSI Manufacturing System and Its Application
Akihisa CHIKAMURA Koji NAKAMAE Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6 ; pp. 1013-1017
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
discrete event simulation, wafer test process, LSI manufacturing, cost, 
 Summary | Full Text:PDF