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IEICE Trans

Keyword : speculative execution

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution
Shimpei SATO Eijiro SASSA Yuta UKON Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/12/01
Vol. E102-A  No. 12 ; pp. 1760-1769
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
circuit design, variable-latency circuit, speculative execution, general-synchronous circuit, timing-error detection, 
 Summary | Full Text:PDF
Potential of Constructive Timing-Violation
Toshinori SATO Itsujiro ARITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 323-330
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
instruction level parallelism, low power design, fault tolerance, timing constraints, speculative execution, 
 Summary | Full Text:PDF
Speculative Execution and Reducing Branch Penalty on a Superscalar Processor
Hideki ANDO Chikako NAKANISHI Hirohisa MACHIDA Tetsuya HARA Masao NAKAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7 ; pp. 1080-1093
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Improved Binary Digital Architectures
Keyword: 
superscalar, VLIW, speculative execution, 
 Summary | Full Text:PDF