Tetsuya HARA


Speculative Execution and Reducing Branch Penalty on a Superscalar Processor
Hideki ANDO Chikako NAKANISHI Hirohisa MACHIDA Tetsuya HARA Masao NAKAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7  pp. 1080-1093
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Improved Binary Digital Architectures
Keyword: 
superscalarVLIWspeculative execution
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