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IEICE Trans

Keyword : transistor sizing

Transistor Sizing of LCD Driver Circuit for Technology Migration
Masanori HASHIMOTO Takahito IJICHI Shingo TAKAHASHI Shuji TSUKIYAMA Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2712-2717
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
technology migration, transistor sizing, LCD driver circuit, 
 Summary | Full Text:PDF
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3251-3257
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
crosstalk noise, capacitive coupling noise, transistor sizing, gate sizing, post-layout optimization, 
 Summary | Full Text:PDF
Experimental Study on Cell-Base High-Performance Datapath Design
Masanori HASHIMOTO Yoshiteru HAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3204-3207
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
datapath design, bit-slice layout, transistor sizing, cell-base design, 
 Summary | Full Text:PDF
Increase in Delay Uncertainty by Performance Optimization
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2799-2802
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
performance optimization, delay increase, statistical timing analysis, delay uncertainty, transistor sizing, 
 Summary | Full Text:PDF
Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2769-2777
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
transistor sizing, low power design, cell-base design, post-layout optimization, gate sizing, 
 Summary | Full Text:PDF
A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing
Sungkun LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/10/01
Vol. E84-A  No. 10 ; pp. 2553-2560
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
buffer insertion, transistor sizing, optimization, 
 Summary | Full Text:PDF
A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2558-2568
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword: 
statistical static timing analysis, static timing analysis, gate resizing, transistor sizing, performance optimization, 
 Summary | Full Text:PDF
Power and Area Minimization by Reorganizing CMOS Complex-Gates
Masayoshi TACHIBANA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Masaaki YAMADA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 312-320
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
VLSI CAD, logic synthesis, complex-gate, transistor sizing, 
 Summary | Full Text:PDF
Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization
Masaaki YAMADA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4 ; pp. 441-446
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: DA/Architecture
Keyword: 
LSI, layout, transistor sizing, low power, CAD, 
 Summary | Full Text:PDF