| Keyword : transistor sizing
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A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing Sungkun LEE Juho KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/10/01
Vol. E84-A
No. 10 ;
pp. 2553-2560
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD Keyword: buffer insertion, transistor sizing, optimization, | | Summary | Full Text:PDF | |
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