IEICE Trans

Masanori HASHIMOTO

A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter Dehua LIANG Jun SHIOMI Noriyuki MIURA Masanori HASHIMOTO Hiromitsu AWANO
Publication: Publication Date: 2022/07/01 Vol. E105-D No. 7 pp. 1273-1282 Type of Manuscript: PAPER Category: Computer System Keyword: EnsembleBloomCA, reservoir computing, cellular automata, Ensemble Bloom Filter,
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Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling Yutaka MASUDA Jun NAGAYAMA TaiYu CHENG Tohru ISHIHARA Yoichi MOMIYAMA Masanori HASHIMOTO
Publication: Publication Date: 2022/03/01 Vol. E105-A No. 3 pp. 509-517 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: critical path isolation, bit-width scaling, voltage over-scaling, approximate computing,
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Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization TaiYu CHENG Yutaka MASUDA Jun NAGAYAMA Yoichi MOMIYAMA Jun CHEN Masanori HASHIMOTO
Publication: Publication Date: 2022/03/01 Vol. E105-A No. 3 pp. 497-508 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: mode-wise voltage-scaling, activation-aware slack assignment, multi-corner multi-mode, downhill simplex method,
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A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA Ryutaro DOI Xu BAI Toshitsugu SAKAMOTO Masanori HASHIMOTO
Publication: Publication Date: 2020/12/01 Vol. E103-A No. 12 pp. 1447-1455 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: via-switch, non-volatile FPGA, crossbar, fault diagnosis,
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MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop Yutaka MASUDA Masanori HASHIMOTO
Publication: Publication Date: 2019/07/01 Vol. E102-A No. 7 pp. 867-877 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: adaptive voltage scaling, activation-aware slack assignment, mean time to failure, timing error predictive FF,
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Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature Takahiro NAKAYAMA Masanori HASHIMOTO
Publication: Publication Date: 2019/07/01 Vol. E102-A No. 7 pp. 914-917 Type of Manuscript: Special Section LETTER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: hold violation, ultra-low temperature, functional test, delay characteristic,
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Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate Wang LIAO Masanori HASHIMOTO
Publication: Publication Date: 2019/04/01 Vol. E102-C No. 4 pp. 296-302 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: soft error rate, chip-level, SRAMs, flip flops, combinational circuits,
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Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble Koichi MITSUNARI Jaehoon YU Takao ONOYE Masanori HASHIMOTO
Publication: Publication Date: 2018/09/01 Vol. E101-A No. 9 pp. 1298-1307 Type of Manuscript: Special Section PAPER (Special Section on Intelligent Transport Systems) Category: Keyword: decision tree ensemble, task scheduling, object detection, machine learning, embedded systems,
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Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors Yutaka MASUDA Takao ONOYE Masanori HASHIMOTO
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 pp. 1452-1463 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: electrical timing error, software-based error detection, EDM transformation, error detection,
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Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator Shoichi IIZUKA Yuma HIGUCHI Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-A No. 12 pp. 2607-2613 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: variation sensor, Ring Oscillator, device-parameter estimation, performance adaptation,
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Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-the-Fly Etching Process Modification Daisuke FUKUDA Kenichi WATANABE Yuji KANAZAWA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 pp. 1467-1474 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: etching, manufacturability, modeling variability,
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Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Hajime SHIMADA Kazutoshi KOBAYASHI Hiroyuki KANBARA Hiroyuki OCHI Takashi IMAGAWA Kazutoshi WAKABAYASHI Masanori HASHIMOTO Takao ONOYE Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2518-2529 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: reconfigurable architecture, soft error, radiation test, behavioral synthesis, state machine,
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A Process and Temperature Tolerant Oscillator-Based True Random Number Generator Takehiko AMAKI Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2393-2399 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: true random number generator, hardware random number generator, oscillator-based random number generator,
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Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm Daisuke FUKUDA Kenichi WATANABE Naoki IDANI Yuji KANAZAWA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 pp. 2373-2382 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: Edge-over-Erosion, CMP, manufacturability, machine learning,
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NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time Hiroaki KONOURA Toshihiro KAMEDA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/07/01 Vol. E97-A No. 7 pp. 1483-1491 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: NBTI, NBTI mitigation, performance degradation, scan path, aging, reliability,
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Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices Hiroaki KONOURA Takashi IMAGAWA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/07/01 Vol. E97-A No. 7 pp. 1468-1482 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: fault avoidance, lifetime enhancement, mean-time-to-failure (MTTF), partial reconfiguration,
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SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects Ryo HARADA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/07/01 Vol. E97-A No. 7 pp. 1461-1467 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: soft error, single event transient (SET), pulse-width, pulse-width modulation, measurement circuit, within-die process variation,
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Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices Toshihiro KAMEDA Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/08/01 Vol. E96-D No. 8 pp. 1624-1631 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Test and Verification Keyword: field test, fault avoidance, coarse-grained reconfigurable device,
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Jitter Amplifier for Oscillator-Based True Random Number Generator Takehiko AMAKI Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/03/01 Vol. E96-A No. 3 pp. 684-696 Type of Manuscript: PAPER Category: Cryptography and Information Security Keyword: true random number generator, jitter,
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Signal-Dependent Analog-to-Digital Conversion Based on MINIMAX Sampling Igors HOMJAKOVS Masanori HASHIMOTO Tetsuya HIROSE Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/02/01 Vol. E96-A No. 2 pp. 459-468 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: signal-dependent sampling, MINIMAX, peak-detection,
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A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning Shuta KIMURA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2292-2300 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: post-silicon tuning, body bias clustering, process variation, body biasing, statistical static timing analysis,
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Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure Yasumichi TAKAI Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2220-2225 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: power gating, on-chip power supply noise, rush current, well structure,
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Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis Takashi ENAMI Takashi SATO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2261-2271 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: power distribution network, decoupling capacitance, timing analysis, statistical static timing analysis, decap insertion, wire sizing,
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Stress Probability Computation for Estimating NBTI-Induced Delay Degradation Hiroaki KONOURA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2545-2553 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: NBTI, stress probability, timing analysis,
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Extracting Device-Parameter Variations with RO-Based Sensors Ken-ichi SHINKAI Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2537-2544 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: variation sensor, manufacturing variability, device-parameter, ring oscillator,
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Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise Takaaki OKUMURA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/10/01 Vol. E94-A No. 10 pp. 1948-1953 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: power supply noise, Flip-Flop, setup time, hold time, timing analysis,
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Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution Ryo HARADA Yukio MITSUYAMA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2417-2423 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: soft error, single event transient (SET), pulse width, measurement circuit,
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Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation Takashi ENAMI Shinyu NINOMIYA Ken-ichi SHINKAI Shinya ABE Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2399-2408 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: statistical timing analysis, clock jitter, setup verification, structural correlation, power supply noise,
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Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation Shinyu NINOMIYA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2441-2446 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: statistical timing analysis, manufacturing variability,
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Gate Delay Estimation in STA under Dynamic Power Supply Noise Takaaki OKUMURA Fumihiro MINAMI Kenji SHIMAZAKI Kimihiko KUWADA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2447-2455 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: power supply noise, gate delay, timing analysis,
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Impact of Self-Heating in Wire Interconnection on Timing Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 388-392 Type of Manuscript: BRIEF PAPER Category: Keyword: interconnect, delay variation, parasitic resistance, thermal, temperature, self-heat, SoC,
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Prediction of Self-Heating in Short Intra-Block Wires Ken-ichi SHINKAI Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/03/01 Vol. E93-A No. 3 pp. 583-594 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: self-heating, temperature, interconnect, local wire, process scaling,
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Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction Hiroshi FUKETA Masanori HASHIMOTO Yukio MITSUYAMA Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3094-3102 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: adaptive speed control, subthreshold circuit, timing error prediction, timing margin variability,
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An Approach for Reducing Leakage Current Variation due to Manufacturing Variability Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3016-3023 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: low power, leakage, gate delay model, variation,
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Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 990-997 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: SSTA, output, transition time, gate delay model, process variation,
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An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability Koichi HAMAMOTO Hiroshi FUKETA Masanori HASHIMOTO Yukio MITSUYAMA Takao ONOYE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/02/01 Vol. E92-C No. 2 pp. 281-285 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: body bias, layout,
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Impact of Well Edge Proximity Effect on Timing Toshiki KANAMOTO Yasuhiro OGASAHARA Keiko NATSUME Kenji YAMAGUCHI Hiroyuki AMISHIRO Tetsuya WATANABE Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3461-3464 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: well edge proximity effect, WPE, delay, timing,
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Area-Efficient Reconfigurable Architecture for Media Processing Yukio MITSUYAMA Kazuma TAKAHASHI Rintaro IMAI Masanori HASHIMOTO Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3651-3662 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: reconfigurable, media processing, multi-standard, area-efficiency, dynamic reconfiguration,
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Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution Shinya ABE Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3481-3487 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: mesh-style clock distribution, clock skew,
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Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration Masanori HASHIMOTO Jangsombatsiri SIRIPORN Akira TSUCHIYA Haikun ZHU Chung-Kuan CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3474-3480 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: eye-diagram, on-chip transmission line, waveform distortion, resistive termination, shunt conductance,
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Timing Analysis Considering Temporal Supply Voltage Fluctuation Masanori HASHIMOTO Junji YAMAGUCHI Takashi SATO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 655-660 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Verification and Timing Analysis Keyword: timing analysis, dynamic power supply noise,
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Timing Analysis Considering Spatial Power/Ground Level Variation Masanori HASHIMOTO Junji YAMAGUCHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2661-2668 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: timing analysis, power supply noise, gate delay model, power/ground level variation,
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Transistor Sizing of LCD Driver Circuit for Technology Migration Masanori HASHIMOTO Takahito IJICHI Shingo TAKAHASHI Shuji TSUKIYAMA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2712-2717 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: technology migration, transistor sizing, LCD driver circuit,
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Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 pp. 1267-1273 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: on-chip transmission-line, termination,
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Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect Yasuhiro OGASAHARA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 724-731 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: signal integrity, interconnect delay, capacitive crosstalk, inductive crosstalk,
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Proposal of Metrics for SSTA Accuracy Evaluation Hiroyuki KOBAYASHI Nobuto ONO Takashi SATO Jiro IWAI Hidenari NAKASHIMA Takaaki OKUMURA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 pp. 808-814 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: statistical static timing analysis, statistical max operation, DFM, SoC,
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Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3585-3593 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: parameter extraction, transmission-line, frequency dependence,
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Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3666-3670 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: interconnect, delay variation, parasitic capacitance, SoC,
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Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design Toshiki KANAMOTO Tatsuhiko IKEDA Akira TSUCHIYA Hidetoshi ONODERA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3560-3568 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: substrate, interconnect, resistance, inductance, SoC,
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On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature Takashi SATO Junji ICHIMIYA Nobuto ONO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3491-3499 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation and Verification Keyword: thermal gradient simulation, leakage power, temperature-dependent leakage power, power calculation, leakage model,
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A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays Shingo TAKAHASHI Shuji TSUKIYAMA Masanori HASHIMOTO Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3538-3545 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: active matrix LCD, CAD tool, column driver, sampling pulse, sampling switch,
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Statistical Analysis of Clock Skew Variation in H-Tree Structure Masanori HASHIMOTO Tomonori YAMAMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3375-3381 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: clock skew, manufacturing variability, environmental variability, transition time constraint, statistical analysis, clock distribution,
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On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design Takashi SATO Junji ICHIMIYA Nobuto ONO Koutaro HACHIYA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3382-3389 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: thermal simulation, thermal gradient, temperature flattening, clock skew, reliability, timing,
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Successive Pad Assignment for Minimizing Supply Voltage Drop Takashi SATO Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3429-3436 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Power/Ground Network Keyword: successive pad assignment (SPA), incremental matrix inversion (IMI), voltage drop, power distribution network,
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Effects of On-Chip Inductance on Power Distribution Grid Atsushi MURAMATSU Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3564-3572 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: power distribution network, on-chip inductance, power supply noise, decoupling capacitance,
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Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance Atsushi KUROKAWA Masanori HASHIMOTO Akira KASEBE Zhangcai HUANG Yun YANG Yasuaki INOUE Ryosuke INAGAKI Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3453-3462 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: capacitance formula, capacitance calculation, capacitance extraction, interconnect capacitance,
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Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 885-891 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: global interconnect, high-speed signaling, performance limitation,
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A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL Takahito MIYAZAKI Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/03/01 Vol. E88-C No. 3 pp. 437-444 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: clock generation PLL, LC oscillator, ring oscillator, performance prediction, jitter, power consumption, chip area,
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Crosstalk Noise Optimization by Post-Layout Transistor Sizing Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3251-3257 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: crosstalk noise, capacitive coupling noise, transistor sizing, gate sizing, post-layout optimization,
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Crosstalk Noise Estimation for Generic RC Trees Masanori HASHIMOTO Masao TAKAHASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2965-2973 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: crosstalk noise, capacitive coupling, noise estimation, signal integrity,
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Experimental Study on Cell-Base High-Performance Datapath Design Masanori HASHIMOTO Yoshiteru HAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3204-3207 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: IP Design Keyword: datapath design, bit-slice layout, transistor sizing, cell-base design,
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Representative Frequency for Interconnect R(f)L(f)C Extraction Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2942-2951 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: interconnect, extraction, frequency-dependent,
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Increase in Delay Uncertainty by Performance Optimization Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2799-2802 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Analysis Keyword: performance optimization, delay increase, statistical timing analysis, delay uncertainty, transistor sizing,
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Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2769-2777 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: transistor sizing, low power design, cell-base design, post-layout optimization, gate sizing,
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A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 pp. 2558-2568 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Performance Optimization Keyword: statistical static timing analysis, static timing analysis, gate resizing, transistor sizing, performance optimization,
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A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits Masanori HASHIMOTO Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/01/25 Vol. E82-A No. 1 pp. 159-166 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: input reordering, transistor reordering, power estimation,
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