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| Keyword : physical design
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Trojan Vulnerability Map: An Efficient Metric for Modeling and Improving the Security Level of Hardware
Mahmoud BAKHSHIZADEH Ali JAHANIAN | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/11/01
Vol. E97-A
No. 11 ;
pp. 2218-2226
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
hardware security, hardware trojan, physical design, | | | Summary | Full Text:PDF | |
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Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model
Yanming JIA Yici CAI Xianlong HONG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A
No. 12 ;
pp. 3783-3792
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
VLSI, buffer insertion, physical design, DFM, dummy fill, | | | Summary | Full Text:PDF | |
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Efficient Routing of Board-Level Optical Clocks for Ultra High-Speed Systems
Chung-Seok (Andy) SEO Abhijit CHATTERJEE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A
No. 6 ;
pp. 1310-1317
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
Category:
Keyword:
clock, optical waveguide, interconnect, physical design, optimization, | | | Summary | Full Text:PDF | |
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