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| Keyword : architecture
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High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications
Sangho YOON Hanho LEE Kihoon LEE | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/04/01
Vol. E93-A
No. 4 ;
pp. 769-777
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
concatenated BCH code, FEC, architecture, optical, | | | Summary | Full Text:PDF | |
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A Low-Power Architecture for Extended Finite State Machines Using Input Gating
Shi-Yu HUANG Chien-Jyh LIU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A
No. 12 ;
pp. 3109-3115
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
low-power, architecture, VLSI design, FSM, gating, synthesis, | | | Summary | Full Text:PDF | |
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Architectural Choices in Large Scale ATM Switches
Jonathan TURNER Naoaki YAMANAKA | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1998/02/25
Vol. E81-B
No. 2 ;
pp. 120-137
Type of Manuscript:
INVITED PAPER (Special Issue on ATM Switching Systems for future B-ISDN)
Category:
Keyword:
ATM, switch, B-ISDN, buffer, architecture, | | | Summary | Full Text:PDF | |
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Functional Elements for Switching Software Based on Object-Oriented Paradigm with UPT as an Example
Fumito SATO Motoo HOSHI Yuji INOUE | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 1992/10/25
Vol. E75-B
No. 10 ;
pp. 1052-1060
Type of Manuscript:
Special Section PAPER (Special Issue on Communication Software Technologies)
Category:
Keyword:
object-oriented, architecture, | | | Summary | Full Text:PDF | |
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