A New Processor Architecture for Digital Signal Transport Systems

Minoru INAMORI  Kenji ISHII  Akihiro TSUTSUI  Kazuhiro SHIRAKAWA  Toshiaki MIYAZAKI  Hiroshi NAKADA  

IEICE TRANSACTIONS on Electronics   Vol.E81-C   No.9   pp.1408-1415
Publication Date: 1998/09/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
processor,  VLSI,  protocol processing,  architecture,  

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This paper proposes a new processor architecture for manipulating the protocols of digital signal transport systems. In order to offer various kinds of telecommunication services, flexibility as well as high performance is required of digital signal transport systems. To realize such systems, this architecture consists of a core CPU, memories, and dedicated application-specific hardware. Software on the core CPU offers flexibility, while the dedicated hardware provides performance. A computer simulation confirms the efficiency of the architecture.