High-Speed Design of Conflictless Name Lookup and Efficient Selective Cache on CCN Router

Atsushi OOKA  Shingo ATA  Kazunari INOUE  Masayuki MURATA  

Publication
IEICE TRANSACTIONS on Communications   Vol.E98-B   No.4   pp.607-620
Publication Date: 2015/04/01
Online ISSN: 1745-1345
DOI: 10.1587/transcom.E98.B.607
Type of Manuscript: PAPER
Category: Network
Keyword: 
future networks,  content-centric networking,  architecture,  router hardware,  content-addressable memory,  bloom filter,  

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Summary: 
Content-centric networking (CCN) is an innovative network architecture that is being considered as a successor to the Internet. In recent years, CCN has received increasing attention from all over the world because its novel technologies (e.g., caching, multicast, aggregating requests) and communication based on names that act as addresses for content have the potential to resolve various problems facing the Internet. To implement these technologies, however, requires routers with performance far superior to that offered by today's Internet routers. Although many researchers have proposed various router components, such as caching and name lookup mechanisms, there are few router-level designs incorporating all the necessary components. The design and evaluation of a complete router is the primary contribution of this paper. We provide a concrete hardware design for a router model that uses three basic tables — forwarding information base (FIB), pending interest table (PIT), and content store (CS) — and incorporates two entities that we propose. One of these entities is the name lookup entity, which looks up a name address within a few cycles from content-addressable memory by use of a Bloom filter; the other is the interest count entity, which counts interest packets that require certain content and selects content worth caching. Our contributions are (1) presenting a proper algorithm for looking up and matching name addresses in CCN communication, (2) proposing a method to process CCN packets in a way that achieves high throughput and very low latency, and (3) demonstrating feasible performance and cost on the basis of a concrete hardware design using distributed content-addressable memory.