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IEICE Trans

Xu BAI

28nm Atom-Switch FPGA: Static Timing Analysis and Evaluation
Xu BAI Ryusuke NEBASHI Makoto MIYAMURA Kazunori FUNAHASHI Naoki BANNO Koichiro OKAMOTO Hideaki NUMATA Noriyuki IGUCHI Tadahiko SUGIBAYASHI Toshitsugu SAKAMOTO Munehiro TADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2022/10/01
Vol. E105-C  No. 10  pp. 627-630
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
FPGA, atom switch, non-volatile, resistive-change memory (RRAM), programmable logic, static timing analysis (STA), 
 Summary | Full Text:PDF
A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA
Ryutaro DOI Xu BAI Toshitsugu SAKAMOTO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2020/12/01
Vol. E103-A  No. 12  pp. 1447-1455
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
via-switch, non-volatile FPGA, crossbar, fault diagnosis, 
 Summary | Full Text:PDF
Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/10/01
Vol. E97-C  No. 10  pp. 1028-1035
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
voltage-mode/current-mode hybrid design, arbitrary two-variable function circuit, fine-grain reconfigurable VLSI, 
 Summary | Full Text:PDF
Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9  pp. 2278-2285
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
Keyword: 
multiple-valued reconfigurable VLSI, fine-grain reconfigurable VLSI, global tree local X-net network, logic-in-memory architecture, 
 Summary | Full Text:PDF
A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/08/01
Vol. E96-C  No. 8  pp. 1083-1093
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
fine-grain reconfigurable VLSI architecture, multiple-valued switch block, binary-controlled current-steering technique, current-source sharing technique, current-mode logic (CML), 
 Summary | Full Text:PDF
A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/07/01
Vol. E96-D  No. 7  pp. 1449-1456
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
multiple-valued data transfer scheme, X-net, multiple-valued current-mode logic, MOS current-mode logic, fine-grain reconfigurable VLSI, 
 Summary | Full Text:PDF