Keyword : fine-grain reconfigurable VLSI


Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/10/01
Vol. E97-C  No. 10 ; pp. 1028-1035
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
voltage-mode/current-mode hybrid designarbitrary two-variable function circuitfine-grain reconfigurable VLSI
 Summary | Full Text:PDF

Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9 ; pp. 2278-2285
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
Keyword: 
multiple-valued reconfigurable VLSIfine-grain reconfigurable VLSIglobal tree local X-net networklogic-in-memory architecture
 Summary | Full Text:PDF

A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme
Xu BAI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/07/01
Vol. E96-D  No. 7 ; pp. 1449-1456
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
multiple-valued data transfer schemeX-netmultiple-valued current-mode logicMOS current-mode logicfine-grain reconfigurable VLSI
 Summary | Full Text:PDF

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits
Nobuaki OKADA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2126-2133
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Application of Multiple-Valued VLSI
Keyword: 
multiple-valued current-mode logicfine-grain reconfigurable VLSIdirect allocationcontrol circuitsequential logic circuit
 Summary | Full Text:PDF

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
Nobuaki OKADA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1437-1443
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
fine-grain reconfigurable VLSImultiple-valued source-coupled logicuniversal literaldirect allocation of CDFGlogic block
 Summary | Full Text:PDF